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Ordering Information
Part Number
FAN3268TMX
Logic
Non-Inverting Channel and Inverting
Channel + Dual Enables
Input Threshold
TTL
Packing Method
2,500 Units on
Tape & Reel
FAN3268TMX_F085
(1)
Non-Inverting Channel and Inverting
Channel + Dual Enables
TTL
2,500 Units on
Tape & Reel
1. Qualified to AEC-Q100
Package Outline
ENA
INA
GND
INB
1
2
3
4
8
7
6
5
ENB
OUTA
VDD
OUTB
Figure 2. Pin Configuration (Top View)
Thermal Characteristics
(2)
Θ JT
Θ JA
Ψ JT
Package
Θ JL
(3)
(4)
(5)
Ψ JB
(6)
(7)
Units
8-Pin Small Outline Integrated Circuit (SOIC)
40
31
89
43
3
°C/W
Notes:
2.
3.
4.
5.
6.
7.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL ( Θ JL ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT ( Θ JT ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA ( Θ JA ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB ( Ψ JB ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 5. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
Psi_JT ( Ψ JT ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 5.
? 2009 Fairchild Semiconductor Corporation
FAN3268 ? Rev. 1.0.3
2
www.fairchildsemi.com
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